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- этимология
Что (кто) такое cache-prise - определение
AWARD
Fermat Prise
secondary cache
![Austek]] A38202; to the right of the processor)](https://commons.wikimedia.org/wiki/Special:FilePath/Motherboard Intel 386.jpg?width=200 "Austek]] A38202; to the right of the processor)")
![[[Motherboard]] of a [[NeXTcube]] computer (1990). At the lower edge of the image left from the middle, there is the CPU [[Motorola 68040]] operated at 25 [[MHz]] with two separate level 1 caches of 4 KiB each on the chip, one for the instructions and one for data. The board has no external L2 cache.](https://commons.wikimedia.org/wiki/Special:FilePath/NeXTcube motherboard.jpg?width=200 "[[Motherboard]] of a [[NeXTcube]] computer (1990). At the lower edge of the image left from the middle, there is the CPU [[Motorola 68040]] operated at 25 [[MHz]] with two separate level 1 caches of 4 KiB each on the chip, one for the instructions and one for data. The board has no external L2 cache.")
DYNAMICALLY MANAGED LOCAL MEMORY THAT MIRRORS MAIN MEMORY IN A MICROPROCESSOR TO REDUCE THE COST OF ACCESS
Level 1 cache; Level 2 cache; Cache line; CPU memory cache; Trace Caches; Trace caches; Cache block; Cache-line; L2 cache; L3 cache; L1 cache; CPU caches; CPU Cache; Data cache; Internal cache; Data Cache; First-level cache; L2-Cache; L1-Cache; Second-level cache; Secondary cache; Tag RAM; Direct mapped; Cpu cache; Instruction cache; L2 Cache; Cache flush; Motherboard cache; Discrete L2 cache; Level 3 cache; VIVT; VIPT; I cache; Processor cache; Internal and external cache; Multi-ported Cache; Smart Cache; CPU cache line; Copy-back; L4 cache; Micro-operation cache; Uop cache; Last level cache; Last Level Cache; Cache eviction; Exclusive CPU cache; Inclusive CPU cache; Exclusive cache; Inclusive cache; Multi-level cache; Multilevel cache; On-chip cache; Cache lines; Shared cache; Non-blocking cache; Branch target cache; Branch target instruction cache; SmartCache; Smart cache; L1d
<memory management> (Or "second level cache", "level two
cache", "L2 cache") A larger, slower cache between the
primary cache and main memory. Whereas the primary cache
is often on the same integrated circuit as the {central
processing unit} (CPU), a secondary cache is usually external.
(1997-06-25)
Web cache
MECHANISM FOR THE TEMPORARY STORAGE (CACHING) OF WEB DOCUMENTS
Web caching; HTTP cache; Browser Cache; Browser Caching; Squirrel (DHT); Squirrel dht; Web caches; Proxy cache; Browser cache; Cache server; Internet cache; Http cache; HTTP caching; Webcache; Cache-Control; Web browser cache; Bypass your cache; Webcaching; List of server-side web caching software; Forward cache; Reverse cache
A Web cache (or HTTP cache) is a system for optimizing the World Wide Web. It is implemented both client-side and server-side.
cache line
DYNAMICALLY MANAGED LOCAL MEMORY THAT MIRRORS MAIN MEMORY IN A MICROPROCESSOR TO REDUCE THE COST OF ACCESS
Level 1 cache; Level 2 cache; Cache line; CPU memory cache; Trace Caches; Trace caches; Cache block; Cache-line; L2 cache; L3 cache; L1 cache; CPU caches; CPU Cache; Data cache; Internal cache; Data Cache; First-level cache; L2-Cache; L1-Cache; Second-level cache; Secondary cache; Tag RAM; Direct mapped; Cpu cache; Instruction cache; L2 Cache; Cache flush; Motherboard cache; Discrete L2 cache; Level 3 cache; VIVT; VIPT; I cache; Processor cache; Internal and external cache; Multi-ported Cache; Smart Cache; CPU cache line; Copy-back; L4 cache; Micro-operation cache; Uop cache; Last level cache; Last Level Cache; Cache eviction; Exclusive CPU cache; Inclusive CPU cache; Exclusive cache; Inclusive cache; Multi-level cache; Multilevel cache; On-chip cache; Cache lines; Shared cache; Non-blocking cache; Branch target cache; Branch target instruction cache; SmartCache; Smart cache; L1d
<storage> (Or cache block) The smallest unit of memory than
can be transferred between the main memory and the cache.
Rather than reading a single word or byte from main memory at
a time, each cache entry is usually holds a certain number of
words, known as a "cache line" or "cache block" and a whole
line is read and cached at once. This takes advantage of the
principle of locality of reference: if one location is read
then nearby locations (particularly following locations) are
likely to be read soon afterward. It can also take advantage
of page-mode DRAM which allows faster access to
consecutive locations.
(1997-01-21)
Википедия
Fermat Prize
The Fermat prize of mathematical research biennially rewards research works in fields where the contributions of Pierre de Fermat have been decisive:
- Statements of variational principles
- Foundations of probability and analytic geometry
- Number theory.
The spirit of the prize is focused on rewarding the results of research accessible to the greatest number of professional mathematicians within these fields. The Fermat prize was created in 1989 and is awarded once every two years in Toulouse by the Institut de Mathématiques de Toulouse. The amount of the Fermat prize has been fixed at 20,000 Euros for the twelfth edition (2011).
